Microarchitect / RTL Design - Network Datapath & MAC Engine
About Architect Labs
Architect is a frontier AI lab for custom silicon. We partner with frontier labs, clouds / neoclouds, physical AI companies, and advanced fabs to tape-out custom chips co-designed for next-generation AI workloads. Our goal is to compress end-to-end software to silicon timelines, and maximize intelligence per watt and per dollar for the world. We are a small exceptional team across silicon, systems, software and frontier AI. Our team have led research teams at nearly every frontier AI lab, and at some of the most complex SoCs in the world.
What You’ll Do
As a Member of the Technical Staff on the RTL Design team at Architect, you’ll own the AI-driven microarchitecture and RTL design of high-performance networking subsystems going into production silicon. You will define, drive, and revise the block-level micro-architecture specification for Ethernet MAC engines, packet processing pipelines, and network datapath logic — ensuring line-rate performance, protocol compliance, and seamless SoC integration.
Core Responsibilities
Own the network datapath RTL end-to-end: from IEEE 802.3-compliant MAC engine design through code generation, lint, CDC, synthesis, and timing closure using our AI-driven design flow.
