RAN Validation Engineer
AST SpaceMobile is building the first and only global cellular broadband network in space to operate directly with standard, unmodified mobile devices based on our extensive IP and patent portfolio and designed for both commercial and government applications. Our engineers and space scientists are on a mission to eliminate the connectivity gaps faced by today’s five billion mobile subscribers and finally bring broadband to the billions who remain unconnected.
Position Overview
We are seeking a Senior FPGA Verification Engineer with 4–8 years of experience to design, develop, and execute comprehensive verification strategies for complex FPGA designs. This role requires strong hands-on expertise in SystemVerilog and UVM, testbench architecture, and cross-functional collaboration with design and system teams.
Key Responsibilities:
- Develop and maintain SystemVerilog/UVM-based verification environments for FPGA block-level and top-level designs
- Create and execute verification plans, directed and constrained-random test scenarios, assertions, and functional coverage
- Perform simulation-based verification of FPGA designs using industry-standard simulators
