Principal Design Validation & Test (DVT) Engineer
About The Role
Celero is seeking an experienced Principal Design Validation & Test (DVT) Engineer to lead post-silicon validation for next-generation coherent DSP ASICs powering AI and hyperscale optical networking. As a key member of our engineering team, you will play a critical role in enabling first silicon, driving silicon characterization, and ensuring product readiness for customer deployment and high-volume production.
This is a highly visible technical leadership role within a fast-paced startup where you will work closely with Architecture, RTL Design, Firmware, Systems, Product Engineering, and customers to solve complex silicon challenges. You will have the opportunity to influence validation strategy, define best practices, and help build our validation infrastructure from the ground up.
What You'll Do
- Lead post-silicon validation and characterization of complex ASICs and SoCs from first silicon through production release.
- Develop comprehensive validation plans covering functionality, performance, interoperability, compliance, stress testing, corner cases, and reliability.
- Enable first silicon bring-up using JTAG, scan, embedded debug features, and board-level diagnostics.
- Validate high-speed interfaces inclu
