IC/RTL Design Engineer
IC/RTL Design Engineer/ Front-End Engineer
About the role. You design and implement the digital front-end RTL at the heart of the chip — including the high-speed datapath that moves data between UCIe and the optical front end. Guided by the interface specs and coding standards, you take blocks from micro-architecture through clean, timing-aware RTL and block-level verification. It's a hands-on role with room to grow your scope as the team and the chip mature.
What you'll do
Develop block-level micro-architecture for your assigned blocks, and contribute to interface and register definitions.
Design and implement front-end RTL blocks in SystemVerilog — datapath elements, the UCIe streaming/RDI adapter, elastic FIFOs, and supporting logic.
Integrate IP and support parameterization for configurability.
Write clean, lint-clean, CDC/RDC-clean RTL that follows the coding and quality standards.
Write block-level test
