Packaging Engineer- Bump Interconnect

We’re seeking an experienced engineer to lead bump interconnect development for advanced semiconductor devices  (2.5D/3D/chiplet/fan-out). 

 

This role spans ubump and C4 bump metallurgy, RDL design and

plating, chip-side and interposer capture pad design rules, OSAT engagement, reliability,

failure analysis, and cross-functional support through package and system productization.

 

Core Responsibilities

• Own end-to-end bump interconnect development for both ubump (micro-bump) and C4

processes, including bump formation, and reflow for use with mass reflow, TCB, and LAB chip

attach for high-performance semiconductor packages.

• Define and own bump metallurgy stacks for ubump (e.g., Cu pillar/SnAg) and C4 (e.g., SAC alloys)

interconnects, including UBM selection and pad finish specifications for both chip-side and

interposer capture pads.

• Develop and own design rules for bump interconnects including pitch, bump diameter, standoff

height, keep-outs, and land pad geometry for both the chip side and interposer or substrate

capture pads.

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