Packaging Engineer- Flip Chip

We're seeking experienced engineers to contribute to flip chip package development and assembly processes for advanced semiconductor devices (2.5D/3D/chiplet/fan-out/flip-chip).

This spans bump metallurgy, substrate integration, reflow and underfill processes, reliability, failure analysis, and cross-functional support through package and system productization.

 

Core Responsibilities:

• Develop and optimize flip chip attach processes including bump formation,

placement, reflow, and underfill for high-performance semiconductor packages.

• Define and manage bump metallurgy stacks (e.g., Cu pillar, SnAg, micro-bumps)

and substrate pad finishes for robust interconnect performance.

• Drive package integration from die to substrate, ensuring alignment, coplanarity,

and yield optimization.

• Evaluate and mitigate assembly risks including warpage, non-wet opens, voiding,

head-in-pillow, and interconnect defects.

• Collaborate with substrate vendors, OSATs, and internal teams to define design

rules (pad pitch, bump pitch, keep-outs, stack-ups).

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