DFT Engineer
๐ง๐ต๐ถ๐ ๐ฟ๐ผ๐น๐ฒ ๐ถ๐ ๐ณ๐ผ๐ฟ ๐ผ๐ป๐ฒ ๐ผ๐ณ ๐๐ต๐ฒ ๐ช๐ฒ๐ฒ๐ธ๐ฑ๐ฎ๐'๐ ๐ฐ๐น๐ถ๐ฒ๐ป๐๐
๐ฆ๐ฎ๐น๐ฎ๐ฟ๐ ๐ฟ๐ฎ๐ป๐ด๐ฒ: ๐ฅ๐ ๐ญ๐ฑ๐ฌ๐ฌ๐ฌ๐ฌ๐ฌ - ๐ฅ๐ ๐ฏ๐ฑ๐ฌ๐ฌ๐ฌ๐ฌ๐ฌ (๐ถ๐ฒ ๐๐ก๐ฅ ๐ญ๐ฑ-๐ฏ๐ฑ ๐๐ฃ๐)
Experience: 7+ yrs
Location: bangalore
Job Type: Full-time
We are looking for an experienced DFT Engineer with strong hands-on expertise in Design for Testability (DFT) for complex ASIC and SoC designs. The role focuses on developing and implementing DFT architectures, scan insertion, scan-chain implementation, MBIST, ATPG, test-pattern generation, and DFT verification.
The ideal candidate will have a strong understanding of semiconductor test methodologies and the ability to own DFT activities across the design lifecycle, from architecture and implementation through pattern generation, verification, coverage analysis, and sign-off.
Requirements
KEY RESPONSIBILITIES
- Develop and implement DFT architectures for complex ASIC and SoC designs.
- Define and implement scan architecture, scan insertion, and scan-chain structures.
- Develop, debug, and validate ATPG patterns for stuck-at, transition, and other fault models.
- Implement and verify MBIST solutions for embedded memories.
- Analyse and improve test coverage, fault simulation results, and pattern quality.
- Perform DFT rule checks and identify a
