GLS verfication engineer
๐ง๐ต๐ถ๐ ๐ฟ๐ผ๐น๐ฒ ๐ถ๐ ๐ณ๐ผ๐ฟ ๐ผ๐ป๐ฒ ๐ผ๐ณ ๐๐ต๐ฒ ๐ช๐ฒ๐ฒ๐ธ๐ฑ๐ฎ๐'๐ ๐ฐ๐น๐ถ๐ฒ๐ป๐๐
๐ฆ๐ฎ๐น๐ฎ๐ฟ๐ ๐ฟ๐ฎ๐ป๐ด๐ฒ: ๐ฅ๐ ๐ฎ๐ฌ๐ฌ๐ฌ๐ฌ๐ฌ๐ฌ - ๐ฅ๐ ๐ด๐ฌ๐ฌ๐ฌ๐ฌ๐ฌ๐ฌ (๐ถ๐ฒ ๐๐ก๐ฅ ๐ฎ๐ฌ-๐ด๐ฌ ๐๐ฃ๐)
Experience: 2+ yrs
Location: Hyderabad, Telangana, India
Job Type: Full-time
As a Design Verification Engineer โ GLS, you will work on gate-level and post-synthesis verification of complex digital designs. You will develop, configure, execute, and debug GLS environments while analysing functional and timing-related failures.
A key part of the role will involve SDF-annotated simulations, where you will investigate timing behaviour and failures across different design stages. You will work closely with RTL, synthesis, Static Timing Analysis (STA), Physical Design, DFT, and other engineering teams to identify the source of issues and drive them through resolution.
You will also contribute to full-chip and subsystem-level verification, execute regression suites, analyse failures, track coverage, and support overall verification closure. The role provides an opportunity to work on complex SoC/ASIC designs and contribute to improving verification methodologies, automation, and debugging efficiency.
Requirements
Key Responsibilities
- Lead Gate-Level Simulation (GLS) and post-synthesis verification activities for complex SoC/ASIC designs.
- Develop, configure, execute, and debug gate-level simulation envir
