RTL Design Engineer
MiddleOn-site (Hyderabad)Salary undisclosed
Required Skills
Python
Job Description
This role is for one of Weekday’s clients
Min Experience: 5+ years
Location: Hyderabad, Bengaluru
JobType: full-time
We are seeking an experienced RTL Design Engineer with 5–11 years of hands-on experience in digital design and semiconductor development. The ideal candidate will have strong expertise in RTL design, microarchitecture, and UPF (Unified Power Format), with a solid understanding of low-power design methodologies and SoC development.
You will be responsible for translating architectural and microarchitectural specifications into robust, synthesizable RTL, collaborating with architecture, verification, physical design, and power teams, and ensuring designs meet functional, performance, area, and power requirements.
Requirements
Key Responsibilities
- Design, develop, and maintain high-quality RTL modules using Verilog/SystemVerilog based on architectural and microarchitectural specifications.
- Work closely with architects to understand requirements and contribute to defining and refining microarchitecture.
- Develop datapaths, control logic, interfaces, state machines, and other digital blocks for complex SoC designs.
- Implement and maintain UPF-based low-power intent, including power domains, isolation strategies, level shifters, retention, power states, and re
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