Senior RTL Design Engineer - CPU & Microarchitecture
๐ง๐ต๐ถ๐ ๐ฟ๐ผ๐น๐ฒ ๐ถ๐ ๐ณ๐ผ๐ฟ ๐ผ๐ป๐ฒ ๐ผ๐ณ ๐๐ต๐ฒ ๐ช๐ฒ๐ฒ๐ธ๐ฑ๐ฎ๐'๐ ๐ฐ๐น๐ถ๐ฒ๐ป๐๐
๐ฆ๐ฎ๐น๐ฎ๐ฟ๐ ๐ฟ๐ฎ๐ป๐ด๐ฒ: ๐ฅ๐ ๐ญ๐ฎ๐ฌ๐ฌ๐ฌ๐ฌ๐ฌ - ๐ฅ๐ ๐ฎ๐ฑ๐ฌ๐ฌ๐ฌ๐ฌ๐ฌ (๐ถ๐ฒ ๐๐ก๐ฅ ๐ญ๐ฎ-๐ฎ๐ฑ ๐๐ฃ๐)
Experience: 5+ yrs
Location: Bengaluru, Hyderabad, Telangana, India
Job Type: Full-time
We are looking for an experienced Senior RTL Design Engineer โ CPU & Microarchitecture to contribute to the design and development of high-performance ASIC and SoC architectures, with a strong focus on CPU cores and processor subsystems.
The ideal candidate will have deep expertise in RTL design, SystemVerilog, CPU microarchitecture, and computer organization, along with practical experience developing complex digital designs for production silicon. You will contribute to architecture implementation, RTL development, verification collaboration, synthesis readiness, and technical debugging across the SoC development lifecycle.
Requirements
KEY RESPONSIBILITIES
- Design, develop, and maintain synthesizable RTL for CPU cores and processor subsystems.
- Translate CPU microarchitecture specifications into efficient and scalable RTL implementations.
- Develop and optimise instruction execution pipelines, hazard handling, branch prediction, and related CPU datapath/control logic.
- Design and integrate L1/L2 cache, MMU, interrupt, and memory subsystem components.</
