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Posted 3d agoโ€ขBengaluru, Karnataka, India

Senior RTL Integration Engineer

SeniorOn-site (Bengaluru)Salary undisclosed
Required Skills
PythonNext.js
Job Description

๐—ง๐—ต๐—ถ๐˜€ ๐—ฟ๐—ผ๐—น๐—ฒ ๐—ถ๐˜€ ๐—ณ๐—ผ๐—ฟ ๐—ผ๐—ป๐—ฒ ๐—ผ๐—ณ ๐˜๐—ต๐—ฒ ๐—ช๐—ฒ๐—ฒ๐—ธ๐—ฑ๐—ฎ๐˜†'๐˜€ ๐—ฐ๐—น๐—ถ๐—ฒ๐—ป๐˜๐˜€

๐—ฆ๐—ฎ๐—น๐—ฎ๐—ฟ๐˜† ๐—ฟ๐—ฎ๐—ป๐—ด๐—ฒ: ๐—ฅ๐˜€ ๐Ÿฎ๐Ÿฌ๐Ÿฌ๐Ÿฌ๐Ÿฌ๐Ÿฌ๐Ÿฌ - ๐—ฅ๐˜€ ๐Ÿฏ๐Ÿฒ๐Ÿฌ๐Ÿฌ๐Ÿฌ๐Ÿฌ๐Ÿฌ (๐—ถ๐—ฒ ๐—œ๐—ก๐—ฅ ๐Ÿฎ๐Ÿฌ-๐Ÿฏ๐Ÿฒ ๐—Ÿ๐—ฃ๐—”)

Experience: 7+ yrs

Location: Bengaluru, Karnataka

Job Type: Full-time

We are looking for a highly experienced RTL Integration Engineer to lead complex SoC and subsystem RTL integration for next-generation semiconductor products. The role requires strong expertise in SystemVerilog/Verilog, digital design, AMBA protocols, static verification, timing constraints, and integration automation.

You will be responsible for integrating multi-million-gate SoCs and complex third-party IPs, ensuring design quality and integration readiness across the development lifecycle. The role involves close collaboration with Architecture, Design Verification, DFT, Synthesis, Physical Design, and other cross-functional teams to resolve integration issues and drive designs toward successful tapeout.

Requirements

KEY RESPONSIBILITIES

  • Lead RTL integration of multi-million-gate SoCs, subsystems, and complex third-party IPs.
  • Integrate IPs such as PCIe, DDR, Ethernet, ARM/RISC-V cores, and other internal or external design blocks using SystemVerilog and Verilog.
  • Configure and assemble SoC interconnect fabrics using AMBA AXI4, AHB, APB, and CHI&n

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