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Posted 3d agoโ€ขBengaluru, Karnataka, India

Senior RTL Integration Engineer

SeniorOn-site (Bengaluru)Salary undisclosed
Required Skills
Python
Job Description

๐—ง๐—ต๐—ถ๐˜€ ๐—ฟ๐—ผ๐—น๐—ฒ ๐—ถ๐˜€ ๐—ณ๐—ผ๐—ฟ ๐—ผ๐—ป๐—ฒ ๐—ผ๐—ณ ๐˜๐—ต๐—ฒ ๐—ช๐—ฒ๐—ฒ๐—ธ๐—ฑ๐—ฎ๐˜†'๐˜€ ๐—ฐ๐—น๐—ถ๐—ฒ๐—ป๐˜๐˜€

๐—ฆ๐—ฎ๐—น๐—ฎ๐—ฟ๐˜† ๐—ฟ๐—ฎ๐—ป๐—ด๐—ฒ: ๐—ฅ๐˜€ ๐Ÿฎ๐Ÿฑ๐Ÿฌ๐Ÿฌ๐Ÿฌ๐Ÿฌ๐Ÿฌ - ๐—ฅ๐˜€ ๐Ÿฐ๐Ÿฌ๐Ÿฌ๐Ÿฌ๐Ÿฌ๐Ÿฌ๐Ÿฌ (๐—ถ๐—ฒ ๐—œ๐—ก๐—ฅ ๐Ÿฎ๐Ÿฑ-๐Ÿฐ๐Ÿฌ ๐—Ÿ๐—ฃ๐—”)

Experience: 7+ yrs

Location: Bengaluru, Karnataka

Job Type: Full-time

We are looking for an experienced Senior RTL Integration Engineer to lead the integration of complex RTL designs and third-party IPs for advanced SoC and semiconductor products. This role requires strong hands-on expertise in RTL Integration and Verilog, along with a solid understanding of digital design, SoC architecture, interconnects, clocking, resets, and design-quality methodologies.

The ideal candidate will be responsible for integrating large and complex RTL blocks, ensuring connectivity and functionality, resolving integration issues, and supporting the design through verification, synthesis, physical design, and tapeout. You will collaborate closely with Architecture, Design Verification, DFT, Synthesis, Physical Design, and other engineering teams to deliver high-quality silicon-ready designs.

Requirements

KEY RESPONSIBILITIES

  • Lead RTL integration for complex SoCs, subsystems, and multi-million-gate designs.
  • Integrate internal and third-party IPs using Verilog/SystemVerilog and established integration methodologies.

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