Design Verification Emulation, Hardware
At River AI, our mission is to create personal AI owned and shaped by each individual. To achieve this, we are rewriting the entire stack from scratch: personal hardware for local inference, bespoke training infrastructure, next-generation UIs, and frontier deep learning research.
Who we are
We are scientists, engineers, and builders from the industry's top tech companies and AI labs. We bring a proven track record of scaling consumer systems for hundreds of millions of users and architecting the pre-training infrastructure behind today's frontier models.
About the Role
We are seeking an emulation-focused design verification engineer to drive IP and SoC verification on emulation platforms. Working with simulation-based DV teams, you will translate architectural and microarchitectural definitions into workloads suited to emulation, then adapt and run those tests. You will partner with DV block owners on debug and emulation-specific closure, providing emulation signoff as an input to overall verification signoff. You will also develop the models and infrastructure needed to support this work.
What You’ll Do
- Verification Strategy & Planning: Translate IP and SoC verification plans into execution strategies, mapping tests to simulation, simulation acceleration, or emulator-hosted verification base
