Physical Design Engineer
๐ง๐ต๐ถ๐ ๐ฟ๐ผ๐น๐ฒ ๐ถ๐ ๐ณ๐ผ๐ฟ ๐ผ๐ป๐ฒ ๐ผ๐ณ ๐๐ต๐ฒ ๐ช๐ฒ๐ฒ๐ธ๐ฑ๐ฎ๐'๐ ๐ฐ๐น๐ถ๐ฒ๐ป๐๐
๐ฆ๐ฎ๐น๐ฎ๐ฟ๐ ๐ฟ๐ฎ๐ป๐ด๐ฒ: ๐ฅ๐ ๐ฎ๐ฌ๐ฌ๐ฌ๐ฌ๐ฌ๐ฌ - ๐ฅ๐ ๐ฑ๐ฌ๐ฌ๐ฌ๐ฌ๐ฌ๐ฌ (๐ถ๐ฒ ๐๐ก๐ฅ ๐ฎ๐ฌ-๐ฑ๐ฌ ๐๐ฃ๐)
Experience: 8+ yrs
Location: Hyderabad, Telangana, India
As a Physical Design Engineer, you will drive the creation of high-performance, low-power silicon solutions by translating complex RTL designs into manufacturable, taped-out chips. Leveraging your deep expertise in VLSI layout, you will optimize placement, clock tree synthesis, and routing while ensuring adherence to timing, power, and area constraints. Your role will involve close collaboration with synthesis, verification, and test teams to deliver designs that meet stringent performance and yield targets. You will also mentor junior engineers and contribute to process improvements that enhance productivity and design quality across the development lifecycle.
Requirements
๐๐ฒ๐ ๐ฅ๐ฒ๐๐ฝ๐ผ๐ป๐๐ถ๐ฏ๐ถ๐น๐ถ๐๐ถ๐ฒ๐
โข Lead the physical design flow from floorplanning to tape-out for ASIC and SoC projects.
โข Perform rigorous static timing analysis and resolve timing violations using industry tools such as Synopsys IC Compiler and PrimeTime.
โข Optimize power consumption through leakage and dynamic power analysis and implement voltage scaling techniques.
โข Interface with floorplanning and clock tree synthesis teams to balance area, timing, and power tradeโoffs.
โข Conduct detailed layout verification using DRC, LVS, and parasitic extraction tools.
